(1) Field of the Invention
The present invention relates to a dynamic reconfigurable computing circuit which can reconfigure the logic configuration dynamically, specifically to a technology of restricting the area of hardware resources required for the reconfiguring.
(2) Description of the Related Art
In recent years, what is called a dynamic reconfigurable computing circuit or a dynamic reconfiguration logic, of which FPGA (Field Programmable Gate Array) or PLG (Programmable Logic Device) is representative, has been developed eagerly. The dynamic reconfigurable computing circuit enables the logic configuration to be reconfigured by a program, making use of the flexibility of software and the speed of hardware.
The FPGA or PLG enables a program to change the connection between transistors, dynamically to some extent.
However, simple FPGAs or PLGs have a problem that they require a large number of hardware resources to perform the reconfiguring, and thus have a large circuit area.
Patent Document 1 identified below discloses one example of technology for solving the problem.
The reconfigurable computing circuit of Patent Document 1 includes a preparatory gate, a switch unit for switching the logic functions for the preparatory gate, a scan path, and a latch unit connected in series to the scan path.
Data is input to the latch unit via the scan path, and then the logic functions are switched by the switch unit in accordance with the data held by the latch unit.
This structure enables the wiring to be shared by the scan path test and by the transfer of the configuration information that is stored in the latch unit to switch the logic functions, thereby reducing the area of hardware.
Patent Document 1: Japanese Patent Application Publication No. H1-289269
However, with the above-described structure of Patent Document 1, to transfer the data to be stored in the latch unit, each register in the scan path needs to store the data.
This causes a problem that the larger the above-described reconfigurable computing circuit is in scale, the larger the area for storing the data that is to be stored in the data registers is, and accordingly the larger the area of the circuit is.